Strain engineering techniques have been studied in the field of semiconductor manufacturing. One application of the strain engineering techniques is for Complementary Metal-Oxide-Semiconductor (CMOS) technology including PMOS and NMOS transistors which respond differently to strains. Particularly, the strain engineering techniques can provide a compressive stress to a channel region of a PMOS transistor to strain the channel region. The strained channel of the PMOS transistor can enhance the mobility of hole carriers so as to improve the operational current of the PMOS transistor.
Conventionally, a silicon nitride (Si3N4) capping layer is formed over a PMOS transistor. The silicon nitride capping layer provides a compressive stress between about 2.4 GPa to of about 3.5 GPa. Due to its high compressive stress, the silicon nitride capping layer stains the channel of the PMOS transistor and enhances the mobility of hole carriers within the channel.
However, when the dimension of semiconductor technology has been shrinking, specially down to 32 nm or less, the compressive stress of the silicon nitride capping layer over the PMOS transistor declines and cannot desirably strain channels of PMOS transistors.
Accordingly, improvements to existing strain engineering techniques are desirable.